
Simple DPLL
===========

The SCT generates a clock which is synchronous to an external clock input.

The DPLL will lock if the input frequency is the same or an integer fraction of
the center frequency of the DPLL. The center frequency is fixed to SCT_clock/32.
You must supply an external clock input to the SCT if you need a center frequency
which cannot be provided directly by the peripheral clock divider.

This state machine design design follows the principle of a TI appnote about the 
74LS297 DPLL device.


The selected settings are: SCT clock = 72 MHz --> Fc = 2.25 MHz
(Please note that the software uses the IRC, and the actual frequency may not
be exact. Use a crystal if you need higher accuracy).

The lock range (Fc/K) is fairly small: With K=64, the range is +/- 35 kHz.

This design uses an edge-triggered phase detector (kd=2).
Clock dividers are: N=32, 2M=N=32.


The following inputs/outputs are used:
CTIN_1 = RESET
CTIN_2 = SIGNAL

CTOUT_0 =  insert
CTOUT_1 =  delete
CTOUT_2 =  down_start
CTOUT_3 =  up_start
CTOUT_4 =  PD
CTOUT_5 =  SCLK